1. Field of the Invention
The present invention relates to a semiconductor memory device and fabrication method thereof, and more particularly, to a semiconductor memory device in which a platinum group metal layer is adopted as a lower electrode, and fabrication method thereof.
2. Description of the Related Art
In order to improve the capacitance of a capacitor of a semiconductor memory device, it is very advantageous to form a lower electrode having a three-dimensional structure that increases the effective surface area of the capacitor while better utilizing available space. However, as the design rule of a semiconductor memory device decreases to below 0.2 μm, there are many problems with formation of a lower electrode having a three-dimensional structure.
FIGS. 1–4 are cross-sectional views for explaining a method of manufacturing a semiconductor memory device including a conventional capacitor. Referring to FIG. 1, after forming an interlevel dielectric layer 13 on a semiconductor substrate 11 such as a silicon substrate, a titanium nitride (TiN) plug 15 is formed within the interlevel dielectric layer 13. The interlevel dielectric layer 13 may be formed of silicon oxide. Then, a silicon nitride (SiN) layer 17 is formed on the interlevel dielectric layer 13 and the titanium nitride plug 15, on top of which a mold layer 19 of silicon oxide is formed. Referring to FIG. 2, the mold layer 19 and the silicon nitride layer 17 are patterned to form a groove 20 that exposes the titanium nitride plug 15. As a result, the mold layer 19 and the silicon nitride layer 17 become a mold pattern 19a and a silicon nitride pattern 17a, respectively. Then, a conductive layer 21 for a lower electrode is provided over the entire surface of the semiconductor substrate 11 on which the groove 20 has been formed. The conductive layer 21 is a platinum group noble metal layer such as a platinum (Pt) layer, a ruthenium (Ru) layer, or an Iridium (Ir) layer. Then, a sacrificial layer 23 for filling the groove 20 is formed over the entire surface of the semiconductor substrate 11 on which the conductive layer 21 has been formed. The sacrificial layer 23 is formed of photo resist or silicon oxide.
Referring to FIG. 3, using the mold pattern 19a as an etching stopper, the sacrificial layer 23 and the conductive layer 21 are sequentially etched to form a sacrificial pattern 23a and a lower electrode 21a. 
Referring to FIG. 4, the lower electrode 21a is formed by removing the sacrificial pattern 23a and the mold pattern 19a by wet etching. Then, a capacitor dielectric layer (not shown) and an upper electrode (not shown) are provided over the lower electrode 21a to complete a capacitor of a semiconductor memory device.
According to a conventional method of manufacturing a semiconductor memory device, since the conductive layer 21, such as a ruthenium layer, exhibits low adhesive strength to the mold pattern 19a and silicon nitride pattern 17a, problems associated therewith occur, for example, the lower electrode 21a may collapse. As a result, the lower electrode 21a is not formed stably.
Furthermore, according to the conventional method, when removing the mold pattern 19a, the adhesive strength between the lower electrode 21a and the silicon nitride pattern 17a is so low that an oxide layer etching solution may penetrate the interface (in a direction of an arrow of FIG. 3) to damage the interlevel dielectric layer 13.